1. Field of the Invention
This invention relates to a semiconductor device, and in particular to a high voltage IC (hereinafter referred to as an “HVIC”).
2. Description of the Background Art
Japanese Patent Application Laid-Open No. 2002-324848 discloses a technique for an HVIC. This technique utilizes a RESURF (REduced SURface Field) effect to achieve a high breakdown voltage, and supplies electric charge to a semiconductor element to which a high potential is applied by using a capacity element for the semiconductor element.
U.S. Pat. No. 4,292,642, for example, describes the RESURF effect. Further, Japanese Patent Application Laid-Open No. 5-190693 (1993) discloses a technique of forming multiple field plates isolated from the surroundings and stabilizing an electric field on a surface of a semiconductor substrate by capacitive coupling between the field plates.
In the technique described in the Japanese Patent Application Laid-Open No. 2002-324848, the capacity element is charged through a diode. Therefore, electric charge accumulated in the capacity element is sometimes insufficient due to a voltage drop of the diode, and desired electric characteristics are sometimes unattainable depending on the required specification of a semiconductor device.
Also in the technique described in the Japanese Patent Application Laid-Open No. 2002-324848, a p-type impurity region which is an anode region of the diode is formed in an n-type semiconductor layer on a p-type semiconductor substrate. Therefore, the p-type impurity region, the n-type semiconductor layer and the p-type semiconductor substrate form a pnp parasitic bipolar transistor which operates to sometimes cause leakage of a charging current to the capacity element, making the desired electric characteristics unattainable.